Aug 29, 2009, 6:02 PM
When I use your Perl code to parse your Verilog file,
Re: [per'l'over] Failed to read the particular block in the given file
the 'always.txt' file is not empty, but it is incomplete.
Your regular expression does not account for consecutive
blank lines within an always block. One improvement might
be to change your '\n\n' to '\n\n\n'. However, this will not
account for 3 consecutive blank lines with your always block.
Verilog code is extremely difficult to parse. The best Perl tool
I have found is the CPAN Verilog::Parser suite. It does a great job
of finding module ports, but I have never tried to parse always
blocks with it.
Obviously, if you could guarantee that your Verilog code were
formatted more consistently, you would have an easier time parsing it.
PS. I realize I am replying to a question which is 1 year old (I just joined this forum).
But, perhaps my answer will be of use to someone searching
(This post was edited by toolic on Sep 10, 2009, 12:37 PM)