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Home: Perl Programming Help: Intermediate: Re: [sid.verycool] match at begin ^ not working for me: Edit Log



BillKSmith
Veteran

Mar 9, 2013, 9:15 AM


Views: 911
Re: [sid.verycool] match at begin ^ not working for me

I have copied the code portion of your post and replaced
the angle bracket code-tags with square bracket tags to
make it legible. I plan to delete it after you edit yours.

I am working your problem and will get back to you later.


CONTENT OF SCRIPT

Code
 #!/usr/bin/perl -w  

BEGIN {undef $/;}


# I TRIED 1ST my $match = "^module.*?$ARGV[2].*?
([\\(;])"; 2ND my $match = "\^module.*?$ARGV[2].*?
([\\(;])"; 3RD my $match = "\\^module.*?$ARGV[2].*?
([\\(;])"


my $match = "module.*?$ARGV[2].*?([\\(;])";
#print "$match";

my $filename = $ARGV[0];

open (INFILE, "<", $filename) or die "Failed to read file $filename : $! \n";

$string = <INFILE>;
close INFILE;



#I ALSO TRIED "$string =~ s/^$match/module $ARGV[1]$1/sg;";

$string =~ s/$match/module $ARGV[1]$1/sg;


open OUTFILE, ">$ARGV[0]" || die "Failed to create $ARGV[0]\n";
print OUTFILE ($string);
close OUTFILE;


what this script does to input file is : CONTENT OF BEFORE SCIPT IS RUN ON FILE

Code
//Verilog HDL for "tt", "hh" "functional"  
// if i write the word here the script goofs up
`timescale 1ps/10fs


module OLD(Y, A, B );
output Y;
input A;
input B;

endmodule

NOW I RUN

Code
script.pl FILE NEW OLD

now the CONTENT OF FILE BECOMES

Code
//Verilog HDL for "tt", "hh" "functional"  
// if i write the word here the script goofs up
`timescale 1ps/10fs


module NEW(Y, A, B );
output Y;
input A;
input B;

endmodule

which is good but if i write the word "module" in the comment line
i.e. CONTENT OF BEFORE SCrIPT IS RUN ON FILE which goofs up

Code
  
//Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
`timescale 1ps/10fs


module OLD(Y, A, B );
output Y;
input A;
input B;

endmodule



Now the contents become

Code
//Verilog HDL for "tt", "hh" "functional"  
// if i write the word module NEW(Y, A, B );
output Y;
input A;
input B;

endmodule

which is unacceptable to me. plz help guys,
Good Luck,
Bill

(This post was edited by BillKSmith on Mar 9, 2013, 9:37 AM)


Edit Log:
Post edited by BillKSmith (Veteran) on Mar 9, 2013, 9:37 AM


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