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Home: Perl Programming Help: Regular Expressions:
Failed to read the particular block in the given file

 



per'l'over
Novice

Aug 5, 2008, 4:19 AM

Post #1 of 2 (3739 views)
Failed to read the particular block in the given file Can't Post

HI all,I have to read the file inputs,outputs,regs,always..of verilog file in the perl and print all the read things ie(inputs,outputs...)into differant corresponding files named correspondingly.I had a code
for this one.But what the problem here is my always file is showing empty.I attached my Perl code here,and also you can see the file that i have to read down the perl code.If u help me out i would be very glad to u.thanks

Code
                                                                      



#!usr/bin/perl

use strict;
use warnings;





open (my $ip_fileh, '<', "pras.v") || die ("unable to open the file pras.v\n"); #open the file


#my $file = do {local $/, <$ip_fileh>}; #read the file in slurp mode for always block


#seek $ip_fileh, 0, 0;
########### output files #############

open (my $op_input_h, '>', "inputs.txt") || die ("unable to open the file inputs.txt\n"); #open the file
open (my $op_output_h, '>', "outputs.txt") || die ("unable to open the file outputs.txt\n"); #open the file
open (my $op_wire_h, '>', "wire.txt") || die ("unable to open the file wire.txt\n"); #open the file
open (my $op_reg_h, '>', "reg.txt") || die ("unable to open the file reg.txt\n"); #open the file
open (my $op_always_h, '>', "always.txt") || die ("unable to open the file always.txt\n"); #open the file


while (<$ip_fileh>){ #read the file line by line

my $str = $_; #assign to a variable

chomp $str; #remove the new line


if ($str =~ m/^\s*(input\s+[^;]*\;)/i){ #match input

print $op_input_h "$1\n"; #print the output

}elsif ($str =~ m/^\s*(output\s+[^;]*\;)/i){ #match output

print $op_output_h "$1\n"; #print the output

}elsif ($str =~ m/^\s*(wire\s+[^;]*\;)/i){ #match wire

print $op_wire_h "$1\n"; #print the output

}elsif ($str =~ m/^\s*(reg\s+[^;]*\;)/i){ #match reg

print $op_reg_h "$1\n"; #print the output

}else{
next;
}

}

seek $ip_fileh, 0, 0; #bring the file handle to the beginning

my $file = do {local $/, <$ip_fileh>}; #read the file in slurp mode for always block


while ($file =~ m/(always\s+\@(?:(?:(?!\n\n).)*)\n\n)/sig){ #match always block

print $op_always_h "$1"; #print the output

}


My verilog file we need to read is


Code
module bmu_csr( /*inputs*/  
sys_clk,sys_reset_n,cbus2bmu_hsel,
cbus2bmu_hwrite,cbus2bmu_haddr,cbus2bmu_hwdata,
cbus2bmu_hready,cbus2bmu_hsize,cbus2bmu_htrans,
bmu_id,
bmu_version,
bmu_revision,
bmu_sw_rst_done,
bmu_active_buf_cnt,
bmu_active_mcast_cnt,
bmu_empty_int_pulse,
bmu_full_int_pulse,
bmu_thres_int_pulse,
bmu_free_err_pulse,
bmu_mcast_empty_int_pulse,
bmu_mcast_full_int_pulse,
bmu_mcast_thres_int_pulse,
bmu_mcast_free_err_pulse,
ucast_alloc_reg_wait,
ucast_alloc_addr,
ucast_free_reg_wait,
ucast_free_addr,
csr_ucast_mem_rdata, csr_ucast_mem_acc_wait,
bmu_free_err_addr,
bmu_curr_buf_cnt,

/* Outputs*/
bmu2cbus_hrdata,

bmu2cbus_hready,
bmu2cbus_hresp, pread, paddr, pwrite, pwdata, pbyte_en,
csr_bmu_en,
csr_bmu_sw_rst,
csr_bmu_max_buf_cnt,
csr_bmu_base_addr,
csr_bmu_buf_size,
csr_bmu_ucast_thres,
csr_bmu_mcast_thres,
bmu_int,
ucast_alloc_addr_rstb,
ucast_free_addr_wstb,
ucast_int_mem_wr, ucast_int_mem_rd, ucast_int_mem_wdata, ucast_int_mem_addr, csr_wdata
);



parameter AHB_ADDR_WIDTH = 32;
parameter AHB_DATA_WIDTH = 32 ;
//Memory-mapped PHB Register addresses (word boundary):


parameter BMU_VERSION_ADDR=8'h00 ;

parameter BMU_CTRL_ADDR=8'h04 ;

parameter BMU_UCAST_CONFIG_ADDR=8'h08 ;

parameter BMU_UCAST_BASEADDR_ADDR=8'h0c ;

parameter BMU_BUF_SIZE_ADDR=8'h10 ;

parameter BMU_BUF_CNT_ADDR=8'h14 ;

parameter BMU_THRES_ADDR=8'h18 ;

parameter BMU_INT_SRC_ADDR=8'h20 ;

parameter BMU_INT_ENABLE_ADDR=8'h24 ;

parameter BMU_ALLOC_CTRL_ADDR=8'h30 ;

parameter BMU_FREE_CTRL_ADDR=8'h34 ;

parameter BMU_INT_MEM_ACCESS_ADDR=12'h100 ;

parameter BMU_FREE_ERROR_ADDR_ADDR=8'h38 ;

parameter BMU_CURR_BUF_CNT_ADDR=8'h3c ;

//Rest vaules

parameter BMU_CTRL_RST=2'b00;

parameter BMU_UCAST_CONFIG_RST=16'd1024;

parameter BMU_UCAST_BASEADDR_RST=32'h0;

parameter BMU_BUF_SIZE_RST=16'd1024;

parameter BMU_THRES_RST=32'd10241024;

parameter BMU_INT_SRC_RST=9'h0;

parameter BMU_INT_ENABLE_RST=9'h0;

parameter BMU_INT_MEM_ACCESS_RST=32'h0;

parameter OKAY = 2'b00,

ERROR = 2'b01,

RETRY = 2'b10,

SPLIT = 2'b11;

parameter IDLE = 2'b00,

BUSY = 2'b01,

NONSEQ = 2'b10,

SEQ = 2'b11;

parameter BYTE = 3'b000,

HWORD = 3'b001,

WORD = 3'b010;

//-------------------------------------------------------------------------
// Port declarations
//------------------------------------------------------------------------
input sys_clk;
input sys_reset_n;
input cbus2bmu_hsel;
input cbus2bmu_hwrite;
input [AHB_ADDR_WIDTH-1:0] cbus2bmu_haddr;
input [AHB_DATA_WIDTH-1:0] cbus2bmu_hwdata;
input [2:0] cbus2bmu_hsize;
input [1:0] cbus2bmu_htrans;
input cbus2bmu_hready;


output [AHB_DATA_WIDTH-1:0] bmu2cbus_hrdata;

output bmu2cbus_hready;
output[1:0] bmu2cbus_hresp;
output [AHB_DATA_WIDTH-1:0] csr_wdata;
output pread;

output [AHB_DATA_WIDTH-1:0] paddr;

output pwrite;

output [AHB_DATA_WIDTH-1:0] pwdata;

output [3:0] pbyte_en;
output bmu_int;

input bmu_empty_int_pulse;
input bmu_full_int_pulse;
input bmu_thres_int_pulse;
input bmu_free_err_pulse;
input bmu_mcast_empty_int_pulse;
input bmu_mcast_full_int_pulse;
input bmu_mcast_thres_int_pulse;
input bmu_mcast_free_err_pulse;
input ucast_alloc_reg_wait;
input [31:0] ucast_alloc_addr;
input ucast_free_reg_wait;
input [31:0] ucast_free_addr;
input [31:0] csr_ucast_mem_rdata;

input csr_ucast_mem_acc_wait;
input [15 : 0] bmu_id;
input [7 : 0] bmu_version;
input [7 : 0] bmu_revision;
output csr_bmu_en;
input bmu_sw_rst_done;
output csr_bmu_sw_rst;
output [15 : 0] csr_bmu_max_buf_cnt;
output [31 : 0] csr_bmu_base_addr;
output [15 : 0] csr_bmu_buf_size;
input [15 : 0] bmu_active_buf_cnt;
input [15 : 0] bmu_active_mcast_cnt;
output [15 : 0] csr_bmu_ucast_thres;
output [15 : 0] csr_bmu_mcast_thres;
output ucast_alloc_addr_rstb;

output ucast_free_addr_wstb;

output ucast_int_mem_wr;
output ucast_int_mem_rd;
output[31:0] ucast_int_mem_wdata;
output[8:0] ucast_int_mem_addr;
input [31 : 0] bmu_free_err_addr;
input [15 : 0] bmu_curr_buf_cnt;
reg csr_bmu_en;
reg csr_bmu_sw_rst;
reg [15 : 0] csr_bmu_max_buf_cnt;
reg [31 : 0] csr_bmu_base_addr;
reg [15 : 0] csr_bmu_buf_size;
reg [15 : 0] csr_bmu_ucast_thres;
reg [15 : 0] csr_bmu_mcast_thres;
reg bmu_int;
reg bmu_empty_int;
reg bmu_full_int;
reg bmu_thres_int;
reg bmu_free_err_int;
reg bmu_mcast_empty_int;
reg bmu_mcast_full_int;
reg bmu_mcast_thres_int;
reg bmu_mcast_free_err_int;
reg bmu_int_en;
reg bmu_empty_int_en;
reg bmu_full_int_en;
reg bmu_thres_int_en;
reg bmu_free_int_en;
reg bmu_mcast_empty_int_en;
reg bmu_mcast_full_int_en;
reg bmu_mcast_thres_int_en;
reg bmu_mcast_free_int_en;
reg [ 31:0] prdata;

reg bmu2cbus_hready ;
reg [31:0] bmu2cbus_hrdata ;
reg data_stage;

wire data_ready;

wire[AHB_DATA_WIDTH-1:0] csr_wdata;


reg pread;

reg [AHB_DATA_WIDTH-1:0] paddr;

reg pwrite;

wire [AHB_DATA_WIDTH-1:0] pwdata;

reg [3:0] pbyte_en;
always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
begin
data_stage <= 0;
end

else if (cbus2bmu_hsel && cbus2bmu_hready && ((cbus2bmu_htrans == SEQ) ||(cbus2bmu_htrans == NONSEQ )))

begin
data_stage <= 1;
end

else if (data_ready)
begin
data_stage <= 0;
end

end



always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
begin
bmu2cbus_hready <= 1;
end

else if (cbus2bmu_hsel && cbus2bmu_hready && (cbus2bmu_htrans == IDLE))

begin
bmu2cbus_hready <= 1;
end
else if (cbus2bmu_hsel && cbus2bmu_hready && ~data_stage )

begin
bmu2cbus_hready <= 0;
end
else if(data_stage && data_ready)
begin
bmu2cbus_hready <= 1;
end
else if( cbus2bmu_hready )
begin
bmu2cbus_hready <= 0;
end
end




assign data_ready = ( ( paddr [10:0]== BMU_ALLOC_CTRL_ADDR) ? !ucast_alloc_reg_wait :
( paddr [10:0]== BMU_FREE_CTRL_ADDR) ? !ucast_free_reg_wait :
( paddr [10:0]== BMU_INT_MEM_ACCESS_ADDR) ? !csr_ucast_mem_acc_wait :
1'b1 );
assign csr_wdata = cbus2bmu_hwdata [31:0];
assign bmu2cbus_hresp = OKAY;
assign pwdata = cbus2bmu_hwdata;




always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
begin
paddr <= 0;
pread <= 0;
pwrite <= 0;
pbyte_en <= 0;
end
else if (cbus2bmu_hsel && cbus2bmu_hready && (cbus2bmu_htrans != IDLE))
begin
paddr <= cbus2bmu_haddr [31:0];
pread <= ! cbus2bmu_hwrite;
pwrite <= cbus2bmu_hwrite;
// byte enable logic based on HSIZE
case (cbus2bmu_hsize)
BYTE:
begin
case (cbus2bmu_haddr [1 : 0])
2'b00:
pbyte_en <= 4'b1000;
2'b01:
pbyte_en <= 4'b0100;
2'b10:
pbyte_en <= 4'b0010;
2'b11:
pbyte_en <= 4'b0001;
endcase
end
HWORD:
begin
case (cbus2bmu_haddr [1])
1'b0:
pbyte_en <= 4'b1100;
1'b1:
pbyte_en <= 4'b0011;
endcase
end
default:
begin
pbyte_en <= 4'b1111;
end
endcase
end
else if (data_stage && cbus2bmu_hready)
begin
paddr <= 0;
pread <= 0;
pwrite <= 0;
pbyte_en <= 0;
end
end

always @ (posedge sys_clk or negedge sys_reset_n) //change
begin
if (sys_reset_n == 0)
begin
bmu2cbus_hrdata <= 0;
end
else if (data_stage)
begin
bmu2cbus_hrdata <=prdata ;
end
end


always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
csr_bmu_en<= BMU_CTRL_RST[0] ;

else if ((paddr [10:0]== BMU_CTRL_ADDR )&& pwrite && (data_stage && data_ready))
begin
csr_bmu_en <= pwdata[0];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
csr_bmu_sw_rst<= 0 ;
else if( bmu_sw_rst_done)
csr_bmu_sw_rst<= 0 ;
else if( (paddr[10:0]== BMU_CTRL_ADDR )&& pwrite && (data_stage && data_ready ))
csr_bmu_sw_rst <= pwdata[1];
end
always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
csr_bmu_max_buf_cnt<= BMU_UCAST_CONFIG_RST[15:0] ;

else if ((paddr [10:0]== BMU_UCAST_CONFIG_ADDR )&& pwrite && (data_stage && data_ready))
begin
csr_bmu_max_buf_cnt <= pwdata[15:0];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
csr_bmu_base_addr<= BMU_UCAST_BASEADDR_RST[31:0] ;

else if ((paddr [10:0]== BMU_UCAST_BASEADDR_ADDR )&& pwrite && (data_stage && data_ready))
begin
csr_bmu_base_addr <= pwdata[31:0];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
csr_bmu_buf_size<= BMU_BUF_SIZE_RST[15:0] ;

else if ((paddr [10:0]== BMU_BUF_SIZE_ADDR )&& pwrite && (data_stage && data_ready))
begin
csr_bmu_buf_size <= pwdata[15:0];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
csr_bmu_ucast_thres<= BMU_THRES_RST[15:0] ;

else if ((paddr [10:0]== BMU_THRES_ADDR )&& pwrite && (data_stage && data_ready))
begin
csr_bmu_ucast_thres <= pwdata[15:0];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
csr_bmu_mcast_thres<= BMU_THRES_RST[31:16] ;

else if ((paddr [10:0]== BMU_THRES_ADDR )&& pwrite && (data_stage && data_ready))
begin
csr_bmu_mcast_thres <= pwdata[31:16];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_int_en<= BMU_INT_ENABLE_RST[0] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_int_en <= pwdata[0];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_empty_int_en<= BMU_INT_ENABLE_RST[1] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_empty_int_en <= pwdata[1];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_full_int_en<= BMU_INT_ENABLE_RST[2] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_full_int_en <= pwdata[2];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_thres_int_en<= BMU_INT_ENABLE_RST[3] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_thres_int_en <= pwdata[3];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_free_int_en<= BMU_INT_ENABLE_RST[4] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_free_int_en <= pwdata[4];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_mcast_empty_int_en<= BMU_INT_ENABLE_RST[5] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_mcast_empty_int_en <= pwdata[5];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_mcast_full_int_en<= BMU_INT_ENABLE_RST[6] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_mcast_full_int_en <= pwdata[6];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_mcast_thres_int_en<= BMU_INT_ENABLE_RST[7] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_mcast_thres_int_en <= pwdata[7];
end
end

always @ (posedge sys_clk or negedge sys_reset_n)
begin
if (sys_reset_n == 0)
bmu_mcast_free_int_en<= BMU_INT_ENABLE_RST[8] ;

else if ((paddr [10:0]== BMU_INT_ENABLE_ADDR )&& pwrite && (data_stage && data_ready))
begin
bmu_mcast_free_int_en <= pwdata[8];
end
end

always @ ( bmu_id or
bmu_version or
bmu_revision or
csr_bmu_en or
csr_bmu_sw_rst or
csr_bmu_max_buf_cnt or
csr_bmu_base_addr or
csr_bmu_buf_size or
bmu_active_buf_cnt or
bmu_active_mcast_cnt or
csr_bmu_ucast_thres or
csr_bmu_mcast_thres or
bmu_int or
bmu_empty_int or
bmu_full_int or
bmu_thres_int or
bmu_free_err_int or
bmu_mcast_empty_int or
bmu_mcast_full_int or
bmu_mcast_thres_int or
bmu_mcast_free_err_int or
bmu_int_en or
bmu_empty_int_en or
bmu_full_int_en or
bmu_thres_int_en or
bmu_free_int_en or
bmu_mcast_empty_int_en or
bmu_mcast_full_int_en or
bmu_mcast_thres_int_en or
bmu_mcast_free_int_en or
ucast_alloc_addr or
ucast_free_addr or
bmu_free_err_addr or
bmu_curr_buf_cnt or
paddr ) begin
prdata = 32 'h0;
if ((paddr [8 :7] == 2'b10 )&& data_ready)
begin
prdata [31:0] ={ csr_ucast_mem_rdata};
end
else
begin
case (paddr[10:0])

BMU_BUF_SIZE_ADDR: prdata[31:0] = {16'b0,csr_bmu_buf_size};
BMU_UCAST_CONFIG_ADDR: prdata[31:0] = {16'b0,csr_bmu_max_buf_cnt};
BMU_ALLOC_CTRL_ADDR: prdata[31:0] = {ucast_alloc_addr};
BMU_CTRL_ADDR: prdata[31:0] = {30'b0,csr_bmu_sw_rst,csr_bmu_en};
BMU_FREE_CTRL_ADDR: prdata[31:0] = {ucast_free_addr};
BMU_THRES_ADDR: prdata[31:0] = {csr_bmu_mcast_thres,csr_bmu_ucast_thres};
BMU_VERSION_ADDR: prdata[31:0] = {bmu_revision,bmu_version,bmu_id};
BMU_FREE_ERROR_ADDR_ADDR: prdata[31:0] = {bmu_free_err_addr};
BMU_INT_ENABLE_ADDR: prdata[31:0] = {23'b0,bmu_mcast_free_int_en,bmu_mcast_thres_int_en,bmu_mcast_full_int_en,bmu_mcast_empty_int_en,bmu_free_int_en,bmu_thres_int_en,bmu_full_int_en,bmu_empty_int_en,bmu_int_en};
BMU_UCAST_BASEADDR_ADDR: prdata[31:0] = {csr_bmu_base_addr};
BMU_CURR_BUF_CNT_ADDR: prdata[31:0] = {16'b0,bmu_curr_buf_cnt};
BMU_BUF_CNT_ADDR: prdata[31:0] = {bmu_active_mcast_cnt,bmu_active_buf_cnt};
BMU_INT_SRC_ADDR: prdata[31:0] = {23'b0,bmu_mcast_free_err_int,bmu_mcast_thres_int,bmu_mcast_full_int,bmu_mcast_empty_int,bmu_free_err_int,bmu_thres_int,bmu_full_int,bmu_empty_int,bmu_int};
default: prdata[31:0] = 32 'h0;
endcase
end
end
//-------------------------------------------------------------------------
// interrupt logic
//-------------------------------------------------------------------------
always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_int <= 0;
else
bmu_int<= bmu_int_en&&(( bmu_empty_int && bmu_empty_int_en ) || ( bmu_full_int && bmu_full_int_en ) || ( bmu_thres_int && bmu_thres_int_en ) || ( bmu_free_err_int && bmu_free_int_en ) || ( bmu_mcast_empty_int && bmu_mcast_empty_int_en ) || ( bmu_mcast_full_int && bmu_mcast_full_int_en ) || ( bmu_mcast_thres_int && bmu_mcast_thres_int_en ) || ( bmu_mcast_free_err_int && bmu_mcast_free_int_en ));
end

// Code for Interrupt Source


always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_empty_int<= 0 ;
else if( bmu_empty_int_pulse)
bmu_empty_int<= 1 ;
else if( pwrite && (paddr[10:0]== BMU_INT_SRC_ADDR )&& pwdata[1]&& (data_stage && data_ready))
bmu_empty_int<= 0 ;
end
always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_full_int<= 0 ;
else if( bmu_full_int_pulse)
bmu_full_int<= 1 ;
else if( pwrite && (paddr[10:0]== BMU_INT_SRC_ADDR )&& pwdata[2]&& (data_stage && data_ready))
bmu_full_int<= 0 ;
end
always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_thres_int<= 0 ;
else if( bmu_thres_int_pulse)
bmu_thres_int<= 1 ;
else if( pwrite && (paddr[10:0]== BMU_INT_SRC_ADDR )&& pwdata[3]&& (data_stage && data_ready))
bmu_thres_int<= 0 ;
end
always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_free_err_int<= 0 ;
else if( bmu_free_err_pulse)
bmu_free_err_int<= 1 ;
else if( pwrite && (paddr[10:0]== BMU_INT_SRC_ADDR )&& pwdata[4]&& (data_stage && data_ready))
bmu_free_err_int<= 0 ;
end
always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_mcast_empty_int<= 0 ;
else if( bmu_mcast_empty_int_pulse)
bmu_mcast_empty_int<= 1 ;
else if( pwrite && (paddr[10:0]== BMU_INT_SRC_ADDR )&& pwdata[5]&& (data_stage && data_ready))
bmu_mcast_empty_int<= 0 ;
end
always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_mcast_full_int<= 0 ;
else if( bmu_mcast_full_int_pulse)
bmu_mcast_full_int<= 1 ;
else if( pwrite && (paddr[10:0]== BMU_INT_SRC_ADDR )&& pwdata[6]&& (data_stage && data_ready))
bmu_mcast_full_int<= 0 ;
end
always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_mcast_thres_int<= 0 ;
else if( bmu_mcast_thres_int_pulse)
bmu_mcast_thres_int<= 1 ;
else if( pwrite && (paddr[10:0]== BMU_INT_SRC_ADDR )&& pwdata[7]&& (data_stage && data_ready))
bmu_mcast_thres_int<= 0 ;
end
always @ (posedge sys_clk or negedge sys_reset_n)

begin
if (sys_reset_n == 0)
bmu_mcast_free_err_int<= 0 ;
else if( bmu_mcast_free_err_pulse)
bmu_mcast_free_err_int<= 1 ;
else if( pwrite && (paddr[10:0]== BMU_INT_SRC_ADDR )&& pwdata[8]&& (data_stage && data_ready))
bmu_mcast_free_err_int<= 0 ;
end
assign ucast_free_addr_wstb = ( (paddr[10:0]== BMU_FREE_CTRL_ADDR )&& pwrite&&data_stage );
assign ucast_alloc_addr_rstb = ( (paddr[10:0]== BMU_ALLOC_CTRL_ADDR )&& pread && data_stage);
assign ucast_int_mem_wdata = pwdata[31:0];
assign ucast_int_mem_addr = paddr[8:0];
endmodule



toolic
User

Aug 29, 2009, 6:02 PM

Post #2 of 2 (3234 views)
Re: [per'l'over] Failed to read the particular block in the given file [In reply to] Can't Post

When I use your Perl code to parse your Verilog file,
the 'always.txt' file is not empty, but it is incomplete.
Your regular expression does not account for consecutive
blank lines within an always block. One improvement might
be to change your '\n\n' to '\n\n\n'. However, this will not
account for 3 consecutive blank lines with your always block.

Verilog code is extremely difficult to parse. The best Perl tool
I have found is the CPAN Verilog::Parser suite. It does a great job
of finding module ports, but I have never tried to parse always
blocks with it.

Obviously, if you could guarantee that your Verilog code were
formatted more consistently, you would have an easier time parsing it.

PS. I realize I am replying to a question which is 1 year old (I just joined this forum).
But, perhaps my answer will be of use to someone searching
this forum.


(This post was edited by toolic on Sep 10, 2009, 12:37 PM)

 
 


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